GNSS receiver technology has changed dramatically since the first reception of a GPS signal. It evolved from complex electrical circuits — partly analog — tracking only one satellite at a time to today’s sophisticated, small multichannel receivers. The core of a modern receiver is contained in one or more highly sophisticated chips that perform all the receiver’s tasks, starting with signal processing, followed by positioning, and often ending at application processing.
GNSS receiver technology has changed dramatically since the first reception of a GPS signal. It evolved from complex electrical circuits — partly analog — tracking only one satellite at a time to today’s sophisticated, small multichannel receivers. The core of a modern receiver is contained in one or more highly sophisticated chips that perform all the receiver’s tasks, starting with signal processing, followed by positioning, and often ending at application processing.
The technology to build these chips is called application-specific integrated circuit (ASIC) technology. Following this approach of receiver design, a manufacturer completely designs the chip from scratch, having the maximum flexibility in the design but also facing tremendous development efforts and costs. By selling a large amount of chipsets, the manufacturer hopes to recover those development costs, enabling the company to offer affordable receivers while still making a profit. However, redesign of a receiver ASIC remains a major task and can only be afforded once every several years.
Nowadays, improvements in software and hardware technology seem to promise reductions in future receiver development costs by using field programmable gate arrays (FPGAs), digital signal processors (DSPs), or even general purpose processors to realize a complete GNSS receiver. The receiver makes use of these predefined hardware structures, which can be configured (in case of an FPGA) or programmed (in case of a processor) by means of software.
For such projects a large number of elaborate tools are available, providing the engineer with a convenient development environment. This, in turn, will lead to greater design productivity and lower development costs. Furthermore, the software approach makes it possible to run field upgrades of the receiver. The obvious question thus arises —with which technology will the future GNSS receiver be built: ASIC, FPGA, DSP, or even a general purpose central processing unit (CPU)?
In this article we try to answer this question as completely as possible by describing future GNSS hardware platforms, focusing on different techniques to realize GNSS tracking and using our background in receiver technology from the algorithmic and application points of view.
(For the rest of this story, please download the complete article using the PDF link above)
